Recently, as a high-speed signal transmission interface, USB 2.0 standard and IEEE 1394 standard has become prevalent.
These interfaces are used in various digital equipment such as personal computers and digital cameras. The USB 2.0 standard and IEEE 1394 standard interfaces adopt a differential signal system in which a pair of data lines is used to transmit a differential signal (differential mode signal), different from a single end transmission system, which has been generally used heretofore.
The differential transmission system has excellent characteristics such that a radiation electromagnetic field generated from the data line is less than that in the single end transmission system and it is hardly affected by exogenous noise. Therefore, it is easy to minimize the amplitude of the signal, and signal transmission can be performed at a higher speed than the single end transmission system by reducing rise time and fall time because of the small amplitude.
FIG. 12 is a circuit diagram of a conventional differential transmission circuit.
The differential transmission circuit shown in FIG. 12 includes a pair of data lines 2 and 4, an output buffer 6 that supplies a differential mode signal to the pair of data lines 2 and 4, and an input buffer 8 that receives the differential mode signal from the pair of data lines 2 and 4. According to such a configuration, an input signal IN to be provided to the output buffer 6 is transmitted to the input buffer 8 via the data lines 2 and 4, and reproduced as an output signal OUT. The differential transmission circuit has such a characteristic that the radiation electromagnetic field generated from the data lines 2 and 4 is less. However, when common noise (common mode noise) is superimposed on the data lines 2 and 4, a relatively large radiation electromagnetic field is generated. In order to reduce the radiation electromagnetic field generated by the common mode noise, as shown in FIG. 12, it is effective to insert a common mode choke coil 10 in the data lines 2 and 4.
The common mode choke coil 10 has such characteristics that an impedance with respect to a differential component (differential mode signal) transmitted on the data lines 2 and 4 is low, and an impedance with respect to an in-phase component (common mode noise) is high. Therefore, by inserting the common mode choke coil 10 in the data lines 2 and 4, the common mode noise transmitted on the pair of data lines 2 and 4 can be intercepted without substantially attenuating the differential mode signal. There has been known a laminated common mode choke coil described in, for example, Japanese Patent Application Laid-open No. H8-203737.
Recently, higher-speed and lower-loss signal transmission characteristics are required for the common mode choke coil. To realize the characteristics, it is effective to widen a conductor width of a spiral conductor constituting the common mode choke coil. However, if the conductor width of the spiral conductor is made wider, a parasitic capacitance between a pair of spiral conductors increases by that much. As the frequency of the signal to be transmitted increases, the parasitic capacitance between the spiral conductors affects largely on signal quality. Therefore, when the frequency of the signal to be transmitted is high, it is essential to reduce the parasitic capacitance between the spiral conductors.
The simplest method for reducing the parasitic capacitance between the spiral conductors is to increase a distance between the spiral conductors and use a resin having a low permittivity as a material of an insulating layer provided between the spiral conductors. However, if the distance between the spiral conductors is simply increased, a height of a chip increases, which contradicts a requirement of low height. Further, when a resin material is used as the material of the insulating layer, a resin insulating layer is formed according to a spin coating method. Therefore, to increase the distance between the spiral conductors, while ensuring sufficient flatness, spin coating needs to be performed between the spiral conductors a plurality of times, to thereby increase the number of steps.
When the distance between the spiral conductors is to be increased, therefore, it is desired to adopt a structure in which extraction conductors are arranged between the spiral conductors, as described in FIG. 14 in Japanese Patent Application Laid-open No. H8-203737. That is, by arranging the extraction conductors, which have been heretofore arranged above and below the spiral conductors, between the spiral conductors, the distance between the spiral conductors can be increased, without increasing the number of insulating layers.
However, if the extraction conductors are arranged between the spiral conductors, the distance between a pair of extraction conductors becomes short and the extraction conductors are adjacent to each other, which causes a decrease of withstand voltage, and short-circuit may occur in some cases. This problem becomes noticeable particularly when the spiral conductor is circular. FIG. 13 is an explanatory schematic plan view, where FIG. 13A indicates a position where extraction electrodes are formed when the spiral conductors are square, and FIGS. 13B and 13C indicate the position where the extraction electrodes are formed when the spiral conductors are circular.
As shown in FIG. 13, a spiral conductor 102 is connected to an extraction conductor 112 via a through hole (not shown) at an inner circumferential end 102a thereof. Likewise, a spiral conductor 104 is connected to an extraction conductor 114 via a through hole (not shown) at an inner circumferential end 104a thereof. To sufficiently increase the distance between the extraction conductors 112 and 114, the positions of the inner circumferential ends 102a and 104a of the spiral conductors 102 and 104 need to be apart from each other sufficiently. At this time, as shown in FIG. 13A, when the spiral conductors 102 and 104 are square, a difference in number of turns in an inner circumference of the spiral conductors 102 and 104 becomes ¼ turn, by setting the distance between the inner circumferential ends 102a and 104a to a distance D1 corresponding to an inner circumference diameter of the spiral conductors 102 and 104.
On the other hand, as shown in FIG. 13B, when the spiral conductors 102 and 104 are circular, if the distance between the inner circumferential ends 102a and 104a is set to a distance D2 corresponding to the inner circumference diameter of the spiral conductors 102 and 104, the difference in number of turns in the inner circumference of the spiral conductors 102 and 104 becomes ½ turn. That is, the difference in number of turns increases as compared to a case that the spiral conductors 102 and 104 are square.
Thus, when the spiral conductors 102 and 104 are circular, symmetrical property is likely to be broken according to a difference of a plan position between the inner circumferential ends 102a and 104a. Therefore, when the spiral conductors 102 and 104 are circular, there is a growing need to bring the plan positions of the inner circumferential ends 102a and 104a close to each other. For example, to set the difference in number of turns in the inner circumference of the spiral conductors 102 and 104 to ¼ the same as in FIG. 13A, as shown in FIG. 13C, the distance between the inner circumferential ends 102a and 104a needs to be decreased considerably. As a result, a distance D3 between the extraction conductors 112 and 114 decreases inevitably, and hence, a decrease in the withstand voltage as well as short-circuit are likely to occur.
Such a problem is not limited to a case that the extraction conductors are arranged between the spiral conductors, and commonly occurs when a pair of extraction conductors is formed on the same insulating layer.